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PTN3361B
HDMI/DVI level shifter with dongle detect support and active DDC buffer
Rev. 02 -- 7 October 2009 Product data sheet
1. General description
The PTN3361B is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals, up to 1.65 Gbit/s per lane. Each of these lanes provides a level-shifting differential buffer to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50 to 3.3 V on the sink side. Additionally, the PTN3361B provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a channel with active buffering and level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using active I2C-bus buffer technology providing capacitive isolation, redriving and level shifting as well as disablement (isolation between source and sink) of the clock and data lines. The low-swing AC-coupled differential input signals to the PTN3361B typically come from a display source with multi-mode I/O, which supports multiple display standards, e.g., DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or HDMI v1.3a specification. By using PTN3361B, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low. See Figure 1. The PTN3361B main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of DisplayPort Standard v1.1 and/or PCI Express Standard v1.1, and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical specifications. The I2C-bus channel actively buffers as well as level-translates the DDC signals for optimal capacitive isolation. Its I2C-bus control block also provides for optional software HDMI dongle detect by issuing a predetermined code sequence upon a read command to an I2C-bus specified address. The PTN3361B also supports power-saving modes in order to minimize current consumption when no display is active or connected. The PTN3361B is a fully featured HDMI as well as DVI level shifter. It is functionally comparable to PTN3360B but provides additional features supporting HDMI dongle detection and active DDC buffering. For HDMI dongles, support of HDMI dongle detection via the DDC channel is mandatory, hence HDMI dongle applications should enable this feature for correct operation in accordance with DisplayPort interoperability guidelines. PTN3361B is powered from a single 3.3 V power supply consuming a small amount of power (90 mW typ.) and is offered in a 48-terminal HVQFN48 package.
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
MULTI-MODE DISPLAY SOURCE OE_N reconfigurable I/Os PCIe PHY ELECTRICAL TMDS coded data PCIe output buffer TX FF TX TMDS coded data PCIe output buffer TX FF TX TMDS coded data PCIe output buffer TX FF TX TMDS clock pattern PCIe output buffer TX FF TX AC-coupled differential pair clock CLOCK LANE OUT_D1+ OUT_D1- IN_D1+ IN_D1- AC-coupled differential pair TMDS data DATA LANE IN_D2+ IN_D2- OUT_D2+ OUT_D2- AC-coupled differential pair TMDS data IN_D3+ DATA LANE IN_D3- OUT_D3+ OUT_D3- AC-coupled differential pair TMDS data IN_D4+ DATA LANE IN_D4- OUT_D4+ OUT_D4-
PTN3361B
0 V to 3.3 V
HPD_SOURCE
HPD_SINK
0 V to 5 V
3.3 V 3.3 V
DDC_EN (0 V to 3.3 V) 5V
SCL_SOURCE 3.3 V DDC I/O (I2C-bus) CONFIGURATION SDA_SOURCE
SCL_SINK 5V
SDA_SINK
002aae053
Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].
Fig 1.
Typical application system diagram
PTN3361B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
DVI/HDMI CONNECTOR 2 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
2. Features
2.1 High-speed TMDS level shifting
I Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals I Pin-programmable pre-emphasis feature I TMDS level shifting operation up to 1.65 Gbit/s per lane (165 MHz character clock) I TMDS level shifting operation up to 2.25 Gbit/s per lane (225 MHz character clock) using pre-emphasis feature I Integrated 50 termination resistors for self-biasing differential inputs I Back-current safe outputs to disallow current when device power is off and monitor is on I Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting
I I I I Integrated active DDC buffering and level shifting (3.3 V source to 5 V sink side) Rise time accelerator on sink-side DDC ports 0 Hz to 400 kHz I2C-bus clock frequency Back-power safe sink-side terminals to disallow backdrive current when power is off or when DDC is not enabled
2.3 HDMI dongle detect support
I Incorporates I2C slave ROM I Responds to DDC read to address 81h with predetermined byte sequence I Feature enabled by pin DDET (must be enabled for correct operation in accordance with DisplayPort interoperability guideline
2.4 HPD level shifting
I HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or from 5 V on the sink side to 3.3 V on the source side I Integrated 200 k pull-down resistor on HPD sink input guarantees `input LOW' when no display is plugged in I Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.5 General
I I I I I I Power supply 3.3 V 10 % ESD resilience to 7 kV HBM, 1 kV CDM Support for optional HDMI dongle detection via DDC/I2C-bus channel Power-saving modes (using output enable) Back-current-safe design on all sink-side main link, DDC and HPD terminals Transparent operation: no re-timing or software configuration required
PTN3361B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
3 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
3. Applications
I DisplayPort to HDMI adapters (must enable DDET) I DisplayPort to DVI adapters required to drive long cables
4. Ordering information
Table 1. Ordering information Package Name PTN3361BBS HVQFN48 Description Version plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; SOT619-1 body 7 x 7 x 0.85 mm Type number
PTN3361B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
4 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
5. Functional diagram
OE_N input bias enable
50 50
PTN3361B
OUT_D4+ OUT_D4-
IN_D4+ IN_D4- input bias enable
50 50
enable
OUT_D3+ OUT_D3-
IN_D3+ IN_D3- input bias enable
50 50
enable
OUT_D2+ OUT_D2-
IN_D2+ IN_D2- input bias enable
50 50
enable
OUT_D1+ OUT_D1-
IN_D1+ IN_D1- enable
HPD level shifter HPD_SOURCE (0 V to 3.3 V) DDC_EN (0 V to 3.3 V) SCL_SOURCE SDA_SOURCE DDET
002aae054
200 k
HPD_SINK (0 V to 5 V)
I2C-BUS SLAVE ROM
DDC BUFFER AND LEVEL SHIFTER
SCL_SINK SDA_SINK
Fig 2.
Functional diagram of PTN3361B
PTN3361B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
5 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
6. Pinning information
6.1 Pinning
48 IN_D4+ 46 VDD 45 IN_D3+ 42 IN_D2+ 40 VDD 39 IN_D1+ 47 IN_D4- 44 IN_D3- 41 IN_D2- 38 IN_D1-
43 GND
terminal 1 index area GND VDD PES0 DDET GND REXT HPD_SOURCE SDA_SOURCE SCL_SOURCE 1 2 3 4 5 6 7 8 9
37 GND 36 GND 35 n.c. 34 n.c. 33 VDD 32 DDC_EN 31 GND 30 HPD_SINK 29 SDA_SINK 28 SCL_SINK 27 GND 26 VDD 25 OE_N GND 24
002aae055
PTN3361BBS
PES1 10 VDD 11 GND 12 OUT_D4+ 13 OUT_D4- 14 VDD 15 OUT_D3+ 16 OUT_D3- 17 GND 18 OUT_D2+ 19 OUT_D2- 20 VDD 21 OUT_D1+ 22 OUT_D1- 23
Transparent top view
HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
Fig 3.
Pin configuration for HVQFN48
PTN3361B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
6 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
6.2 Pin description
Table 2. Symbol OE_N Pin description Pin 25 Type 3.3 V low-voltage CMOS single-ended input Description Output Enable and power saving function for high-speed differential level shifter path. When OE_N = HIGH: IN_Dx termination = high-impedance OUT_Dx outputs = high-impedance; zero output current When OE_N = LOW: IN_Dx termination = 50 OUT_Dx outputs = active IN_D4+ 48 Self-biasing differential input Low-swing differential input from display source with PCI Express electrical signalling. IN_D4+ makes a differential pair with IN_D4-. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D4- makes a differential pair with IN_D4+. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D3+ makes a differential pair with IN_D3-. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D3- makes a differential pair with IN_D3+. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D2+ makes a differential pair with IN_D2-. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D2- makes a differential pair with IN_D2+. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D1+ makes a differential pair with IN_D1-. The input to this pin must be AC coupled externally.
OE_N, IN_Dx and OUT_Dx signals
IN_D4-
47
Self-biasing differential input
IN_D3+
45
Self-biasing differential input
IN_D3-
44
Self-biasing differential input
IN_D2+
42
Self-biasing differential input
IN_D2-
41
Self-biasing differential input
IN_D1+
39
Self-biasing differential input
PTN3361B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
7 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
Pin description ...continued Pin 38 Type Self-biasing differential input Description Low-swing differential input from display source with PCI Express electrical signalling. IN_D1- makes a differential pair with IN_D1+. The input to this pin must be AC coupled externally. HDMI compliant TMDS output. OUT_D4+ makes a differential pair with OUT_D4-. OUT_D4+ is in phase with IN_D4+. HDMI compliant TMDS output. OUT_D4- makes a differential pair with OUT_D4+. OUT_D4- is in phase with IN_D4-. HDMI compliant TMDS output. OUT_D3+ makes a differential pair with OUT_D3-. OUT_D3+ is in phase with IN_D3+. HDMI compliant TMDS output. OUT_D3- makes a differential pair with OUT_D3+. OUT_D3- is in phase with IN_D3-. HDMI compliant TMDS output. OUT_D2+ makes a differential pair with OUT_D2-. OUT_D2+ is in phase with IN_D2+. HDMI compliant TMDS output. OUT_D2- makes a differential pair with OUT_D2+. OUT_D2- is in phase with IN_D2-. HDMI compliant TMDS output. OUT_D1+ makes a differential pair with OUT_D1-. OUT_D1+ is in phase with IN_D1+. HDMI compliant TMDS output. OUT_D1- makes a differential pair with OUT_D1+. OUT_D1- is in phase with IN_D1-. 0 V to 5 V (nominal) input signal. This signal comes from the DVI or HDMI sink. A HIGH value indicates that the sink is connected; a LOW value indicates that the sink is disconnected. HPD_SINK is pulled down by an integrated 200 k pull-down resistor. 0 V to 3.3 V (nominal) output signal. This is level-shifted version of the HPD_SINK signal. 3.3 V source-side DDC clock I/O. Pulled up by external termination to 3.3 V. 3.3 V source-side DDC data I/O. Pulled up by external termination to 3.3 V. 5 V sink-side DDC clock I/O. Pulled up by external termination to 5 V. Provides rise time acceleration for LOW-to-HIGH transitions. 5 V sink-side DDC data I/O. Pulled up by external termination to 5 V. Provides rise time acceleration for LOW-to-HIGH transitions.
Table 2. Symbol IN_D1-
OUT_D4+
13
TMDS differential output TMDS differential output TMDS differential output TMDS differential output TMDS differential output TMDS differential output TMDS differential output TMDS differential output
OUT_D4-
14
OUT_D3+
16
OUT_D3-
17
OUT_D2+
19
OUT_D2-
20
OUT_D1+
22
OUT_D1-
23
HPD and DDC signals HPD_SINK 30 5 V CMOS single-ended input
HPD_SOURCE 7 SCL_SOURCE 9 SDA_SOURCE 8 SCL_SINK 28
3.3 V CMOS single-ended output single-ended 3.3 V open-drain DDC I/O single-ended 3.3 V open-drain DDC I/O single-ended 5 V open-drain DDC I/O single-ended 5 V open-drain DDC I/O
SDA_SINK
29
PTN3361B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
8 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
Pin description ...continued Pin 32 Type 3.3 V CMOS input Description Enables the DDC buffer and level shifter. When DDC_EN = LOW, buffer/level shifter is disabled. When DDC_EN = HIGH, buffer and level shifter are enabled.
Table 2. Symbol DDC_EN
Supply and ground VDD 3.3 V DC supply 2, 11, 15, 21, 26, 33, 40, 46 ground 1, 5, 12, 18, 24, 27, 31, 36, 37, 43 6 analog I/O Supply ground. All GND pins must be connected to ground for proper operation. Supply voltage; 3.3 V 10 %.
VCC GND[1]
Feature control signals REXT Current sense port used to provide an accurate current reference for the differential outputs OUT_Dx. For best output voltage swing accuracy, use of a 10 k resistor (1 % tolerance) from this terminal to GND is recommended. May also be left open-circuit or tied to either VDD or GND. See Section 7.2 for details. Dongle detect enable input. When HIGH, the dongle detect function via I2C is active. When used in an HDMI dongle, this pin must be tied HIGH for correct operation in accordance with DisplayPort interoperability guidelines. When used in a DVI dongle, this pin must be tied LOW. When LOW, the dongle detect function will not respond to an I2C-bus command. Must be tied to GND or VDD either directly or via a resistor. Note that this pin may not be left open-circuit. Programming pins to activate the pre-emphasis feature of the TMDS differential outputs. See Section 7.3 for details. Must be tied either to GND or VDD either directly or via a resistor. To disable pre-emphasis, connect both to GND (PES[1:0] = 00b). PES[1:0] = 11b is reserved for testing purposes and should not be used in normal application. Note that these pins may not be left open-circuit. Not connected. May be left open-circuit or tied to GND or VDD either directly or via a resistor.
DDET
4
3.3 V input
PES1 PES0
10 3
3.3 V CMOS input 3.3 V CMOS input
Miscellaneous n.c. 34, 35 no connection to the die
[1]
HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
(c) NXP B.V. 2009. All rights reserved.
PTN3361B_2
Product data sheet
Rev. 02 -- 7 October 2009
9 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
7. Functional description
Refer to Figure 2 "Functional diagram of PTN3361B". The PTN3361B level shifts four lanes of low-swing AC-coupled differential input signals to DVI and HDMI compliant open-drain current-steering differential output signals, up to 1.65 Gbit/s per lane. Speed of operation and cable length drive may be extended (by using the programmable pre-emphasis feature) to up to 2.25 Gbit/s per lane. It has integrated 50 termination resistors for AC-coupled differential input signals. An enable signal OE_N can be used to turn off the TMDS inputs and outputs, thereby minimizing power consumption. The TMDS outputs are back-power safe to disallow current flow from a powered sink while the PTN3361B is unpowered. The PTN3361B's DDC channel provides active level shifting and buffering, allowing 3.3 V source-side termination and 5 V sink-side termination. The sink-side DDC ports are equipped with a rise time accelerator enabling drive of long cables or high bus capacitance. This enables the system designer to isolate bus capacitance to meet HDMI DDC version 1.3a distance specification. Furthermore, the DDC channel is augmented with an I2C-bus slave ROM device that provides optional HDMI dongle detect response, which can be enabled by dongle detect signal DDET. The PTN3361B offers back-power safe sink-side I/Os to disallow backdrive current from the DDC clock and data lines when power is off or when DDC is not enabled. An enable signal DCC_EN enables the DDC level shifter block. Remark: When used in an HDMI dongle, the DDET function must be enabled for correct operation in accordance with DisplayPort interoperability guidelines. When used in a DVI dongle, the DDET function must be disabled. The PTN3361B also provides voltage translation for the Hot Plug Detect (HPD) signal from 0 V to 5 V on the sink side to 0 V to 3.3 V on the source side. The PTN3361B does not re-time any data. It contains no state machines except for the DDC/I2C-bus block. No inputs or outputs of the device are latched or clocked. Because the PTN3361B acts as a transparent level shifter, no reset is required.
7.1 Enable and disable features
PTN3361B offers different ways to enable or disable functionality, using the Output Enable (OE_N) and DDC Enable (DDC_EN) inputs. Whenever the PTN3361B is disabled, the device will be in Standby mode and power consumption will be minimal; otherwise the PTN3361B will be in Active mode and power consumption will be nominal. These two inputs each affect the operation of PTN3361B differently: OE_N affects only the TMDS channels, and DDC_EN affects only the DDC channel. HPD_SINK does not affect either of the channels. The following sections and truth table describe their detailed operation.
7.1.1 Hot plug detect
The HPD channel of PTN3361B functions as a level-shifting buffer to pass the HPD logic signal from the display sink device (via input HPD_SINK) on to the display source device (via output HPD_SOURCE). The output logic state of HPD_SOURCE output always follows the logic state of input HPD_SINK, regardless of whether the device is in Active or Standby mode.
PTN3361B_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
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PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
7.1.2 Output Enable function (OE_N)
When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully functional. Input termination resistors are enabled and the internal bias circuits are turned on. When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a high-impedance state and drive zero output current. The IN_Dx input buffers are disabled and IN_Dx termination is disabled. Power consumption is minimized. Remark: Note that OE_N has no influence on the HPD_SINK input, HPD_SOURCE output, or the SCL and SDA level shifters. OE_N only affects the high-speed TMDS channel.
7.1.3 DDC channel enable function (DDC_EN)
The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never change state during an I2C-bus operation. Note that disabling DDC_EN during a bus operation will hang the bus, while enabling DDC_EN during bus traffic would corrupt the I2C-bus operation. Hence, DDC_EN should only be toggled while the bus is idle. (See I2C-bus specification).
PTN3361B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
11 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
7.1.4 Enable/disable truth table
Table 3. Inputs HPD_SINK OE_N
[1] [2]
HPD_SINK, OE_N and DDC_EN enabling truth table Channels DDC_EN IN_Dx LOW HIGH OUT_Dx[3] DDC[4] high-impedance SDA_SINK connected to SDA_SOURCE and SCL_SINK connected to SCL_SOURCE high-impedance SDA_SINK connected to SDA_SOURCE and SCL_SINK connected to SCL_SOURCE high-impedance SDA_SINK connected to SDA_SOURCE and SCL_SINK connected to SCL_SOURCE high-impedance SDA_SINK connected to SDA_SOURCE and SCL_SINK connected to SCL_SOURCE HPD_SOURCE[5] LOW LOW Active; DDC disabled Active; DDC enabled Mode
LOW LOW
LOW LOW
50 termination enabled to VRX(bias) 50 termination enabled to VRX(bias)
LOW LOW
HIGH HIGH
LOW HIGH
high-impedance high-impedance
high-impedance; zero output current high-impedance; zero output current
LOW LOW
Standby Standby; DDC enabled
HIGH HIGH
LOW LOW
LOW HIGH
50 termination enabled to VRX(bias) 50 termination enabled to VRX(bias)
HIGH HIGH
Active; DDC disabled Active; DDC enabled
HIGH HIGH
HIGH HIGH
LOW HIGH
high-impedance high-impedance
high-impedance; zero output current high-impedance; zero output current
HIGH HIGH
Standby Standby; DDC enabled
[1] [2] [3] [4] [5]
A HIGH level on input OE_N disables only the TMDS channels. A LOW level on input DDC_EN disables only the DDC channel. OUT_Dx channels `enabled' means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching. DDC channel `enabled' means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE. The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.
PTN3361B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
12 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
7.2 Analog current reference
The REXT pin (pin 6) is an analog current sense port used to provide an accurate current reference for the differential outputs OUT_Dx. For best output voltage swing accuracy, use of a 10 k resistor (1 % tolerance) connected between this terminal and GND is recommended. If an external 10 k 1 % resistor is not used, this pin can be left open-circuit, or connected to GND or VDD, either directly (0 ) or using pull-up or pull-down resistors of value less than 10 k. In any of these cases, the output will function normally but at reduced accuracy over voltage and temperature of the following parameters: output levels (VOL), differential output voltage swing, and rise and fall time accuracy.
7.3 Programmable pre-emphasis
PTN3361B includes an optional programmable pre-emphasis feature, allowing adaptor or motherboard PCB designers to extend speed performance or support longer cable drive. The pre-emphasis feature, when enabled, adds a selectable amount of pre-emphasis to each bit transition by injecting a momentary current pulse (typically 200 ps to 400 ps long) to help overcome cable or trace losses. Pre-emphasis is not needed for normal HDMI operation at speeds below 1.65 Gbit/s and is not required to meet eye diagram compliance. At the user's discretion, it can be enabled in order to provide additional signal boost in difficult or lossy signaling environments such as long cables or lossy media. It should be noted that by enabling pre-emphasis, in addition to the AC effect of the pre-emphasis pulse on the signal transition, also a constant DC current is added in order to provide the necessary headroom, which will affect VOH and VOL static levels. This should be taken into account when designing for HDMI or DVI single-ended (DC) voltage compliance. For full HDMI or DVI compliance in normal applications, the default mode (pre-emphasis off) is recommended. The pre-emphasis feature is programmed by means of two CMOS input pins, PES1 and PES0, according to Table 4:
Table 4. 0 0 1 1
[1]
PTN3361B pre-emphasis logic table PES0 (pin 3) 0 1 0 1 Level 0 dB (default 3.5 dB (150 %) 6 dB (200 %) Test mode[1]
PES1 (pin 10)
Should not be used in normal application.
7.4 Backdrive current protection
The PTN3361B is designed for backdrive prevention on all sink-side TMDS outputs, sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where the display is connected and powered, but the PTN3361B is unpowered. In these cases, the PTN3361B will sink no more than a negligible amount of leakage current, and will block the display (sink) termination network from driving the power supply of the PTN3361B or that of the inactive DVI or HDMI source.
PTN3361B_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
13 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
7.5 Active DDC buffer with rise time accelerator
The PTN3361B DDC channel, besides providing 3.3 V to 5 V level shifting, includes active buffering and rise time acceleration which allows up to 18 meters bus extension for reliable DDC applications. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) line as well as the rise time accelerator on the sink-side port (SCL_SINK and SDA_SINK) enabling the bus to drive a load up to 1400 pF or distance of 18 m on port A, and 400 pF on the source-side port (SCL_SOURCE and SCA_SOURCE). Using the PTN3361B for DVI or HDMI level shifting enables the system designer to isolate bus capacitance to meet HDMI DDC version 1.3 distance specification. The SDA and SCL pins are overvoltage tolerant and are high-impedance when the PTN3361B is unpowered or when DDC_EN is LOW. PTN3361B has rise time accelerators on the sink-side port (SCL_SINK and SDA_SINK) only. During positive bus transitions on the sink-side port, a current source is switched on to quickly slew the SCL_SINK and SDA_SINK lines HIGH once the 5 V DDC bus VIL threshold level of around 1.5 V is exceeded, and turns off as the 5 V DDC bus VIH threshold voltage of approximately 3.5 V is approached.
7.6 I2C-bus based HDMI dongle detection
The PTN3361B includes an on-board I2C-bus slave ROM which provides a means to detect the presence of an HDMI dongle by the system through the DDC channel, accessible via ports SDA_SOURCE and SCL_SOURCE. This allows system vendors to detect HDMI dongle presence through the already available DDC/I2C-bus port using a predetermined bus sequence. Please see Section 8 for more information. For the I2C-bus HDMI Dongle Detect function to be active, input pin DDET (dongle detect) should be tied HIGH. When DDET is LOW, the PTN3361B will not respond to an I2C-bus command. When used in an HDMI dongle, the DDET function must be enabled for correct operation in accordance with DisplayPort interoperability guidelines. When used in a DVI dongle, the DDET function must be disabled. The HDMI dongle detection is accomplished by accessing the PTN3361B on-board I2C-bus slave ROM using a simple sequential I2C-bus Read operation as described below.
7.6.1 Slave address
bit 7 1 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 R/W
slave address
002aad340
R = 1; W = 0
Fig 4.
PTN3361B slave address
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7.6.2 Read operation
The slave device address of PTN3361B is 80h. PTN3361B will respond to a Read command to slave address 81h (PTN3361B will respond with an ACK to a Write command to address 80h). Following the Read command, the PTN3361B will respond with the contents of its internal ROM, as a sequence of 16 bytes, for as long as the master continues to issue clock edges with an acknowledge after each byte. The 16-byte sequence represents the `DP-HDMI ADAPTOR' symbol converted to ASCII and is documented in Table 5. The PTN3361B auto-increments its internal ROM address pointer (0h through Fh) as long as it continues to receive clock edges from the master with an acknowledge after each byte. If the master continues to issue clock edges past the 16th byte, the PTN3361B will respond with a data byte of FFh. If the master does not acknowledge a received byte, the PTN3361B internal address pointer will be reset to 0 and a new Read sequence should be started by the master. Access to the 16-byte is by sequential read only as described above; there is no random-access possible to any specific byte in the ROM.
Table 5. DisplayPort - HDMI Adaptor Detection ROM content 0 44 1 50 2 2D 3 48 4 44 5 4D 6 49 7 20 8 41 9 44 A 41 B 50 C 54 D 4F E 52 F 04
Internal pointer offset (hex) Data (hex) Table 6.
HDMI dongle detect transaction sequence outline Transmitting 7 6 0 5 0 4 0 master master slave master slave master master master slave slave master slave : : slave master master data byte at offset 15 data byte at offset 1 data byte at offset 0 1 0 0 0 0 0 0 1 word address offset data byte 1 0 0 0 0 Bit 3 2 1 R/W Status Master optional optional optional optional mandatory mandatory mandatory mandatory mandatory Slave mandatory mandatory mandatory mandatory mandatory mandatory -
Phase I2C transaction 1 2 3 4 5 6 7 8 9 10 11 12 13 : 40 41 42 START Write command Acknowledge Word address offset Acknowledge STOP START Read command Acknowledge Read data Acknowledge Read data : : Read data Not Acknowledge STOP
Remark: If the slave does not acknowledge the above transaction sequence, the entire sequence should be retried by the source.
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7.7 Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
7.7.1 Bit transfer
One data bit is transferred during each clock phase. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 5).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 5.
Bit transfer
7.7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). See Figure 6.
SDA
SCL S START condition P STOP condition
mba608
Fig 6.
Definition of START and STOP conditions.
7.7.3 System configuration
An I2C-bus device generating a message is a `transmitter', a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'. See Figure 7.
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SDA SCL
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
002aaa381
Fig 7.
System configuration
7.7.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating as acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement
002aaa987
9
Fig 8.
Acknowledgement on the I2C-bus
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8. Application design-in information
8.1 Dongle or cable adaptor detect discovery mechanism
The PTN3361B supports the source-side dongle detect discovery mechanism described in VESA DisplayPort Interoperability Guideline Version 1.1. When a source-side cable adaptor is plugged into a multi-mode source device that supports multiple standards such as DisplayPort, DVI and HDMI, a discovery mechanism is needed for the multi-mode source to configure itself for outputting DisplayPort, DVI or HDMI compliant signals through the dongle or cable adaptor. The discovery mechanism ensures that a multi-mode source device only sends either DVI or HDMI signals when a valid DVI or HDMI cable adaptor is present. The VESA Interoperability Guideline recommends that a multi-mode source to power up with both DDC and AUX CH disabled. After initialization, the source device can use a variety of mechanisms to decide whether a dongle or cable adaptor is present by detecting pin 13 on the DisplayPort connector. Depending on the voltage level detected at pin 13, the source configures itself either:
* as a DVI or HDMI source (see below paragraph for detection between DVI and HDMI),
and enables DDC, while keeping AUX CH disabled, or
* as a DisplayPort source and enables AUX CH, while keeping DDC disabled.
The monitoring of the voltage level on pin 13 by a multi-mode source device is optional. A multi-mode source may also e.g. attempt an AUX CH read transaction and, if the transaction fails, a DDC transaction to discover the presence/absence of a cable adaptor. Furthermore, a source that supports both DVI and HDMI can discover whether a DVI or HDMI dongle or cable adaptor is present by using a variety of discovery procedures. One possible method is to check the voltage level of pin 14 of the DisplayPort connector. Pin 14 also carries CEC signal used for HDMI. Please note that other HDMI devices on the CEC line may be momentarily pulling down pin 14 as a part of CEC protocol. The VESA Interoperability Guideline recommends that a multi-mode source should distinguish a source-side HDMI cable adaptor from a DVI cable adaptor by checking the DDC buffer ID as described in Section 7.6 "I2C-bus based HDMI dongle detection". While it is optional for a multi-mode source to use the I2C-bus based HDMI dongle detection mechanism, it is mandatory for HDMI dongle or cable adaptor to respond to the I2C-bus read command described in Section 7.7. The PTN3361B provides an integrated I2C-bus slave ROM to support this mandatory HDMI dongle detect mechanism for HDMI dongles. For a DisplayPort-to-HDMI source-side dongle or cable adaptor, DDET must be tied HIGH to enable the I2C-bus based HDMI dongle detection response function of PTN3361B. For a DisplayPort-to-DVI sink-side dongle or cable adaptor, DDET must be tied LOW to disable the function.
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9. Limiting values
Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI Tstg VESD Parameter supply voltage input voltage storage temperature electrostatic discharge voltage HBM CDM
[1] [2]
Conditions 3.3 V CMOS inputs 5.0 V CMOS inputs
Min -0.3 -0.3 -0.3 -65 -
Max +4.6 VDD + 0.5 6.0 +150 7000 1000
Unit V V V C V V
[1] [2]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged-Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Recommended operating conditions
Table 8. Symbol VDD VI VI(AV) Rref(ext) Tamb
[1] [2]
Recommended operating conditions Parameter supply voltage input voltage average input voltage external reference resistance ambient temperature 3.3 V CMOS inputs 5.0 V CMOS inputs IN_Dn+, IN_Dn- inputs connected between pin REXT (pin 6) and GND operating in free air
[1] [2]
Conditions
Min 3.0 0 0 -40
Typ 3.3 0 10 1 % -
Max 3.6 3.6 5.5 +85
Unit V V V V k C
Input signals to these pins must be AC-coupled. Operation without external reference resistor is possible but will result in reduced output voltage swing accuracy. For details, see Section 7.2.
10.1 Current consumption
Table 9. Symbol IDD Current consumption Parameter supply current Conditions OE_N = 1 and DDC_EN = 0; Standby mode OE_N = 0; Active mode Min Typ 27 Max 2 50 Unit mA mA
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11. Characteristics
11.1 Differential inputs
Table 10. Symbol UI VRX_DIFFp-p TRX_EYE Vi(cm)M(AC) ZRX_DC VRX(bias) ZI(se) Differential input characteristics for IN_Dx signals Parameter unit interval[1] minimum eye width at IN_Dx input pair includes all frequencies above 30 kHz
[4]
Conditions
[2] [3]
Min 600 0.175 0.8 40
[5]
Typ 50 1.2 -
Max 4000 1.200 100 60 1.4 -
Unit ps V UI mV V k
differential input peak-to-peak voltage receiver eye time peak common-mode input voltage (AC) DC input impedance bias receiver voltage single-ended input impedance inputs in high-impedance state
1.0 100
[6]
[1] [2] [3] [4] [5] [6]
UI (unit interval) = tbit (bit time). UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 1.65 Gbit/s per lane. Nominal UI at 1.65 Gbit/s = 606 ps. VRX_DIFFp-p = 2 x |VRX_D+ - VRX_D-|. Applies to IN_Dx signals. Vi(cm)M(AC) = |VRX_D+ + VRX_D-| / 2 - VRX(cm). VRX(cm) = DC (avg) of |VRX_D+ + VRX_D-| / 2. Intended to limit power-up stress on chip set's PCIe output buffers. Differential inputs will switch to a high-impedance state when OE_N is HIGH.
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11.2 Differential outputs
The level shifter's differential outputs are designed to meet HDMI version 1.3 and DVI version 1.0 specifications.
Table 11. Symbol VOH(se) VOL(se) VO(se) Differential output characteristics for OUT_Dx signals Parameter single-ended HIGH-level output voltage single-ended LOW-level output voltage single-ended output voltage variation Conditions PES[1:0] = 00b PES[1:0] = 00b logic 1 and logic 0 state applied respectively to differential inputs IN_Dn; Rref(ext) connected; see Table 8 single-ended 20 % to 80 % 80 % to 20 % intra-pair inter-pair tjit
[1] [2] [3] [4] [5] [6]
[4] [5] [6] [1]
Min
Typ
Max
Unit
VTT - 0.01 VTT
VTT + 0.01 V
[2]
VTT - 0.60 VTT - 0.50 VTT - 0.40 V 450 500 600 mV
[3]
IOZ tr tf tsk
OFF-state output current rise time fall time skew time jitter time
75 75 -
-
10 240 240 10 250 7.4
A ps ps ps ps ps
jitter contribution
VTT is the DC termination voltage in the HDMI or DVI sink. VTT is nominally 3.3 V. The open-drain output pulls down from VTT. Swing down from TMDS termination voltage (3.3 V 10 %). This differential skew budget is in addition to the skew presented between IN_D+ and IN_D- paired input pins. This lane-to-lane skew budget is in addition to skew between differential input pairs. Jitter budget for differential signals as they pass through the level shifter.
11.3 HPD_SINK input, HPD_SOURCE output
Table 12. Symbol VIH VIL ILI VOH VOL tPD tt Rpd
[1] [2] [3] [4]
HPD characteristics Parameter HIGH-level input voltage LOW-level input voltage input leakage current HIGH-level output voltage LOW-level output voltage propagation delay transition time pull-down resistance Conditions HPD_SINK HPD_SINK HPD_SINK HPD_SOURCE HPD_SOURCE from HPD_SINK to HPD_SOURCE; 50 % to 50 % HPD_SOURCE rise/fall; 10 % to 90 % HPD_SINK input pull-down resistor
[2] [1]
Min 2.0 0 2.5 0 1 100
Typ 5.0 200
Max 5.3 0.8 15 VDD 0.2 200 20 300
Unit V V A V V ns ns k
[3] [4]
Low-speed input changes state on cable plug/unplug. Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time. Time required to transition from VOH to VOL or from VOL to VOH. Guarantees HPD_SINK is LOW when no display is plugged in.
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11.4 OE_N, DDC_EN and DDET inputs
Table 13. Symbol VIH VIL ILI
[1]
OE_N, DDC_EN and DDET input characteristics Parameter HIGH-level input voltage LOW-level input voltage input leakage current OE_N pin
[1]
Conditions
Min 2.0 -
Typ -
Max 0.8 10
Unit V V A
Measured with input at VIH maximum and VIL minimum.
11.5 DDC characteristics
Table 14. DDC characteristics VDD = 3.0 V to 3.3 V Symbol VIH VIL VILc ILI IIL VOL VOL-VILc Parameter HIGH-level input voltage LOW-level input voltage contention LOW-level input voltage input leakage current LOW-level input current LOW-level output voltage difference between LOW-level output and LOW-level input voltage contention input/output capacitance VI = 3.6 V VI = 0.2 V IOL = 100 A or 6 mA guaranteed by design Conditions Min 0.7VDD -0.5 -0.5 0.47 Typ 0.4 0.52 Max +0.3VDD 1 10 0.6 70 Unit V V V A A V mV Input and output SCL_SOURCE and SDA_SOURCE
Cio
VI = 3 V or 0 V; VDD = 3.3 V VI = 3 V or 0 V; VDD = 0 V
1.5 -0.5
6 6 0.1 6 6
7 7 5.5 +1.5 1 10 0.2 7 7 -
pF pF V V A A V pF pF mA
Input and output SDA_SINK and SCL_SINK VIH VIL ILI IIL VOL Cio HIGH-level input voltage LOW-level input voltage input leakage current LOW-level input current LOW-level output voltage input/output capacitance VDD = VI = 5.5 V VI = 0.2 V IOL = 6 mA VI = 3 V or 0 V; VDD = 3.3 V VI = 3 V or 0 V; VDD = 0 V Itrt(pu) transient boosted pull-up current VDD = 4.5 V; slew rate = 1.25 V/s
-
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12. Package outline
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm
SOT619-1
D
B
A
terminal 1 index area A E A1 c
detail X
e1 e 13 L 12 25 e
1/2 e
C b 24 vMCAB wMC y1 C y
Eh
1/2 e
e2
1 terminal 1 index area 48 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 7.1 6.9 Dh 5.25 4.95 E (1) 7.1 6.9 Eh 5.25 4.95 e 0.5 37
36
X 2.5 scale e1 5.5 e2 5.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT619-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18
Fig 9.
PTN3361B_2
Package outline SOT619-1 (HVQFN48)
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13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 10) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 15 and 16
Table 15. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 16. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 10.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 10. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 17. Acronym CDM CEC DDC DVI EMI ESD HBM HDMI HPD I2C-bus I/O NMOS ROM TMDS VESA Abbreviations Description Charged-Device Model Consumer Electronics Control Data Display Channel Digital Visual Interface ElectroMagnetic Interference ElectroStatic Discharge Human Body Model High-Definition Multimedia Interface Hot Plug Detect Inter-IC bus Input/Output Negative-channel Metal-Oxide Semiconductor Read-Only Memory Transition Minimized Differential Signaling Video Electronic Standards Association
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15. Revision history
Table 18. Revision history Release date 20091007 Data sheet status Product data sheet Change notice Supersedes PTN3361B_1 Document ID PTN3361B_2 Modifications: PTN3361B_1
*
Table 11 "Differential output characteristics for OUT_Dx signals", Table note [6]: deleted second sentence Product data sheet -
20090929
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16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
16.4 Licenses
Purchase of NXP ICs with HDMI technology Use of an NXP IC with HDMI technology in equipment that complies with the HDMI standard requires a license from HDMI Licensing LLC, 1060 E. Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: admin@hdmi.org.
16.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PTN3361B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 7 October 2009
28 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
18. Contents
1 2 2.1 2.2 2.3 2.4 2.5 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.7 7.7.1 7.7.2 7.7.3 7.7.4 8 8.1 9 10 10.1 11 11.1 11.2 11.3 11.4 11.5 12 13 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 High-speed TMDS level shifting . . . . . . . . . . . . 3 DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 HDMI dongle detect support. . . . . . . . . . . . . . . 3 HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . 10 Enable and disable features . . . . . . . . . . . . . . 10 Hot plug detect . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Enable function (OE_N) . . . . . . . . . . . 11 DDC channel enable function (DDC_EN). . . . 11 Enable/disable truth table . . . . . . . . . . . . . . . . 12 Analog current reference . . . . . . . . . . . . . . . . 13 Programmable pre-emphasis . . . . . . . . . . . . . 13 Backdrive current protection . . . . . . . . . . . . . . 13 Active DDC buffer with rise time accelerator . 14 I2C-bus based HDMI dongle detection . . . . . . 14 Slave address . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read operation . . . . . . . . . . . . . . . . . . . . . . . . 15 Characteristics of the I2C-bus . . . . . . . . . . . . . 16 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 START and STOP conditions . . . . . . . . . . . . . 16 System configuration . . . . . . . . . . . . . . . . . . . 16 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application design-in information . . . . . . . . . 18 Dongle or cable adaptor detect discovery mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19 Recommended operating conditions. . . . . . . 19 Current consumption . . . . . . . . . . . . . . . . . . . 19 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 20 Differential inputs . . . . . . . . . . . . . . . . . . . . . . 20 Differential outputs . . . . . . . . . . . . . . . . . . . . . 21 HPD_SINK input, HPD_SOURCE output . . . . 21 OE_N, DDC_EN and DDET inputs. . . . . . . . . 22 DDC characteristics . . . . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Soldering of SMD packages . . . . . . . . . . . . . . 24 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 24 25 26 27 28 28 28 28 28 28 28 29
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 October 2009 Document identifier: PTN3361B_2

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